Nicholas West

Finally updated the other pages, and added all the images with new formatting!

I made the background less nauseating, added button looking things, and updated some of the text!

Added a nice skeumorphic-ish background and re-learned css because it's been a while...

Updated the docs even more!

Documentation is started! I've made some improvements to master and slave mode, and I've documented how master can be used. Although writing documentation sucks... I think I'll choose not to write it for the slave mode.

Either way, soon I should have a video demo ready, and it can be shipped!

I've made some improvements to the master implementation, now you can select the SPI speed with the switches. Although for some reason the 7 segment display glows now... doesn't change the fact that it works.

Tomorrow I'll try to improve the slave module. I don't think I'll add support for the other SPI modes before shipping I'm afraid, since I want to move on to my next project sooner rather than later.

Master mode works! It's both transmitting and receiving correctly. This demo is running pretty slowly, but that's an issue of the code I wrote to drive it, and could totally be improved in an actual non-test implementation. Either way, with a few improvements I'll ship this!

The master mode implementation is almost done! Now it's on to verification and running it in hardware. After that, it's probably ship time!

FIFO version works! I've managed to get it to speeds of 480 kB/s running a simple echo (see screenshot), and that's just on the base 100 MHz system clock. In an actual implementation, it could probably go quite a bit higher, as I have a good amount of slack on the timing reports. From here, I'll probably try to clean up the organization a bit and separate the modules out a little more as to make them a bit more interchangeable, before adding AXI bus support then adding a master mode version. Who cares about supporting SPI mode 1, 2, and 3 after all...

Making lots of good progress on the version with FIFOs, now on to the debugging step!

I've finally added the repo and made it all public! Along with that, I've started to focus in on what I want this project to be. Since I want to make a custom SoC over the summer (and probably longer who am I kidding), I now want to provide myself some useful tools for when I do. Both in the form of learning and because SPI is a pretty important format to support. Because of that, I'll next try to focus on making a mode 0 slave with FIFOs, then a master, hopefully capable of supporting all modes. Only time will tell!
For the actual code, I've made some improvements, made the modules more flexible, and added reset support where it's needed.

It works! This is just a mode zero slave for now, but hopefully I can extend the functionality and add stuff like FIFOs and other modes soon. I'll also upload it to GitHub soon, once I figure out a way to make it play nicely with Vivado