Nicholas West

It is officially done!! I've added normalization to the vectors, so now it does the perspective divide in hardware! Now, it's time to move on the the V2, albiet without summer of making. It's been fun! I've also written up a quick github readme, and will do the demo video ASAP. Thanks to all who supported this <3

The matrix processor works!!! I'm pretty tempted to ship it right now since university is heating up and this is 99% of the actual math, but I should hold off and do the most that I possibly can!

I added fixed-point support since it's required to normalize the coordinates (and the intrinsic perspective divide... I should look more into the why coords are between -1 and 1 after that but for now this is ok)
Tomorrow the goal is to FINALLY actually normalize the output coordinates then (if I have the time) multiply them with screen size to get it in raster space. Wish me luck!

Two things primarily done today.
First off I finished the divider, which will be used for the perspective divide/normalization of verts.
Second off, I improved the test code for the matrix processor itself, so now it 100% really truly works in theory!

Next up I'll add normalization to the matrix processor, although that'll kinda be a pain since it means adding fixed point support after that step. I'll try to speedrun learning fixed point arithmetic tomorrow, then get it done as fast as possible! The deadline is coming up after all, and I still have to port all this to FPGA!

The matrix processor is almost done! I'm just debugging one more issue, then it'll be all good. I also uncovered an issue in my functional model, turns out I messed up and was pre-multiplying rather than post-multiplying the matrices like intended. That's fixed now though. After I work out one more bug with this section of things, it'll be on to the rasterizer!

Sorry for the lack of updates! I'm starting uni so even more busy... hopefully I'll finish this before the deadline lmao.
That aside, I've made good progress on actually implementing the matrix processor. I haven't added fixed point support just yet, but I've decided on a Q16.16 format, since it both doesn't really matter and Q16.16 is a good mix between range and precision. I also want to add optional saturation arithmetic, since having triangles that would normally be ok suddenly clip to behind you is not acceptable. That aside, right now I've mostly just focused on actually adding the math support beyond just loads.

Another update! Same as last time for the most part, life has been busy. That aside, I refactored some of the HDL to make it easier to see how it'll synthesize. I've started using the Get it done then make it good philosophy, since I'm starting uni in a week, so I'll have to hustle then polish it later. That aside, I've also added semi-proper memory interfacing. Since this'll run on the Basys 3, I'll add a wrapper at the top level for all the memory stuff, even if I want to eventually use AXI.

Progress update! I haven't gotten too much done because I've been busy with life, but I've started working on the matrix processing unit. That's the part that'll handle the majority of the multiplications. So far I have a good idea of the FSM that'll control the whole thing, and I think it should be done soon-ish? After that I can move on to the hard part, the clipper/rasterizer. Fingers crossed this is done before the end of SoM!

First devlog!!! The functional model of the GPU works! Basically, before going straight to hardware, I wanted to make a simple python implementation to actually understand the algorithms, and this is the semi-complete version of that.
Although it doesn't support stuff like shading and texturing yet, I think I'll just go with this and put it into hardware for now since the SoM deadline is creeping ever closer...
There are some visual bugs, but I think (for the most part) they are caused by floating point errors and no pixel subsampling, which will not be the case in hardware.

Shoutout LonePi for making music to keep me sane while making this

Finally updated the other pages, and added all the images with new formatting!

I made the background less nauseating, added button looking things, and updated some of the text!

Added a nice skeumorphic-ish background and re-learned css because it's been a while...

Updated the docs even more!

Documentation is started! I've made some improvements to master and slave mode, and I've documented how master can be used. Although writing documentation sucks... I think I'll choose not to write it for the slave mode.

Either way, soon I should have a video demo ready, and it can be shipped!

I've made some improvements to the master implementation, now you can select the SPI speed with the switches. Although for some reason the 7 segment display glows now... doesn't change the fact that it works.

Tomorrow I'll try to improve the slave module. I don't think I'll add support for the other SPI modes before shipping I'm afraid, since I want to move on to my next project sooner rather than later.

Master mode works! It's both transmitting and receiving correctly. This demo is running pretty slowly, but that's an issue of the code I wrote to drive it, and could totally be improved in an actual non-test implementation. Either way, with a few improvements I'll ship this!

The master mode implementation is almost done! Now it's on to verification and running it in hardware. After that, it's probably ship time!

FIFO version works! I've managed to get it to speeds of 480 kB/s running a simple echo (see screenshot), and that's just on the base 100 MHz system clock. In an actual implementation, it could probably go quite a bit higher, as I have a good amount of slack on the timing reports. From here, I'll probably try to clean up the organization a bit and separate the modules out a little more as to make them a bit more interchangeable, before adding AXI bus support then adding a master mode version. Who cares about supporting SPI mode 1, 2, and 3 after all...

Making lots of good progress on the version with FIFOs, now on to the debugging step!

I've finally added the repo and made it all public! Along with that, I've started to focus in on what I want this project to be. Since I want to make a custom SoC over the summer (and probably longer who am I kidding), I now want to provide myself some useful tools for when I do. Both in the form of learning and because SPI is a pretty important format to support. Because of that, I'll next try to focus on making a mode 0 slave with FIFOs, then a master, hopefully capable of supporting all modes. Only time will tell!
For the actual code, I've made some improvements, made the modules more flexible, and added reset support where it's needed.

It works! This is just a mode zero slave for now, but hopefully I can extend the functionality and add stuff like FIFOs and other modes soon. I'll also upload it to GitHub soon, once I figure out a way to make it play nicely with Vivado