8 bit CPU

8 bit CPU

10 devlogs
14h 50m
Created by Arca

A custom 8-bit CPU architecture designed in Logisim, aimed at (mostly) having feature parity with the 6502

Timeline

Earned sticker

added memory address register and memory data register, also realised that a mux is a bunch of tri state buffers connected together

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Arca
Arca
1h 5m 1 day ago

Finally found time to work on it again! the jump buffer is done

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Arca
Arca
1h 26m 2 months ago

ALU is done. I added in extra flags because why not add flags? everyone likes flags. One for every pin of the accumulator and four general purpose flags too. Also logisim is glitchy now, the circuit decides whether it'll work or not depending on how and where you place it. yay.

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Arca
Arca
4h 29m 2 months ago

Uhhhh i may have broken logisim

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ALU is now mostly complete!

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Arca
Arca
1h 42m 3 months ago

So it turns out I way overcomplicated bit shifters and I can just do this. Was messing about with muxes and d-type flip flops and tri-state buffers and all that and turns out they can all be replaced by the wires here.

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Instruction fetcher is done. It uses the ring counter to fetch the opcode and operand into registers.

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Arca
Arca
2h 53m 3 months ago

Here's a cool 8 bit register with increment + decrement inputs and carry + borrow outputs too! This allows you to make a 16 bit register pretty easily, which I might use 74LS193 counter ICs are pretty cool I guess.

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Added a ring counter

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Arca
Arca
1h 24m 3 months ago

8-bit registers! And they're made out of logic gates only!

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