Please sign in to access this page

Full size image

Studying Verilog and RISC-V assembly!

Studying Verilog and RISC-V assembly!

0 devlogs

0h 0m

Created by E.

Studying for my upcoming 'Intro to CompArch' exam and mastering Verilog and RISC-V

Followers

Puppy Eyes

No followers yet

Ship Your Project

Orpheus Yap

Get ready!

Once you ship this you can't edit the description of the project, but you'll be able to add more devlogs and re-ship it as you add new features!

Ship Requirements Checklist

Your project must meet ALL these requirements before it can be shipped.

You must have at least one devlog
Project must have a repository link.
Project must have a raw GitHub documentation link.
Project must have a demo link.
Project must have a valid description (at least 30 characters).
Project must have a banner image (not from a Devlog).
Previous ship event must be paid out before shipping again.
Project must have at least 1 hour of tracked time since last ship.

Link Verification

Look, I'm not going through airtable to check your links so here's some automated checks. I hope it's bug free.

Ready to check your links...

Link Status:

Edit Project Links

I confirm that:

I've verified my project links are working correctly
My project is complete and ready to be shipped
I understand that shipping is permanent and cannot be undone